abbr. SJ GMU
ISSN 2657-5841 (printed)
ISSN 2657-6988 (online)
DOI: 10.26408
High-Speed Binary-to-Residue Converter Design Using 2-Bit Segmentation of the Input Word
Robert Smyk*1 
https://orcid.org/0000-0001-9365-4633 Maciej Czyżak2 https://orcid.org/0000-0002-2249-1619
* Corresponding author
1
Gdańsk University of Technology, 11/12 Gabriela Narutowicza Street, 80-233 Gdańsk, Poland, e-mail: robert.smyk@pg.edu.pl
2
The University of Applied Sciences in Elbląg, 1 Wojska Polskiego Street, 82-300 Elbląg, Poland
Abstract:
In this paper a new approach to the design of the high-speed binary-to-residue converter is proposed that allows the attaining of high pipelining rates by eliminating memories used in modulo m generators. The converter algorithm uses segmentation of the input binary word into 2-bit segments. The use and effects of the input word segmentation for the synthesis of converters for five-bit moduli are presented. For the number represented by each segment, the modulo m reduction using a segment modulo m generator is performed. The use of 2-bit segments substantially reduces the hardware amount of the layer of input modulo m generators. The generated residues are added using the multi-operand modulo m adder based on the carry-save adder (CSA) tree, reduction of the number represented by the output CSA tree vectors to the 2m range and fast two-operand modulo m additions. Hardware amount and time delay analyses are also included.
Keywords:
Binary-to-residue conversion, residue number system, FPGA
Issue:
Pages:
42
56
Doi:
Submitted:
02.06.2022
Accepted:
21.07.2022
Published:
31.12.2022
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This article is an open access article distributed under a Creative Commoms Attribution (CCBY 4.0) licence
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Robert Smyk